Electric interconnects between upper and lower surfaces of a semiconductor substrate are used in the vertical integration of semiconductor devices. The interconnects are formed by vertical vias in the wafer, especially so-called through-silicon vias. To produce the through-wafer interconnects, contact holes are etched in the semiconductor substrate and subsequently filled with an electrically conductive material, which can especially be a metal. The substrate is thinned from the rear side by grinding and polishing until the electrically conductive material in the via hole is exposed. The substrates can be stacked, and the corresponding contact pads can be connected permanently by means of electrically conductive solder or the like. Through-wafer interconnects having diameters of typically about 20 μm to 200 μm can be formed by etching larger recesses having inclined sidewalls.
US 2007/048994 A1 discloses methods for forming through-wafer interconnects and structures resulting therefrom. A substrate is provided with a dielectric layer, a pad on the dielectric layer, and a passivation layer. An aperture is formed through the passivation layer and the pad into the substrate. An insulative layer is deposited in the aperture, followed by a conductive layer and a conductive fill.
DE 10 2007 034 306 describes a through-wafer interconnect which is formed by a via hole in a semiconductor layer and a metallization in an opening of a further semiconductor layer. The semiconductor layers are separated by an isolation layer.